The present invention relates to a semiconductor integrated circuit that forms a differential output circuit for outputting signals to another semiconductor integrated circuits.
FIG. 1 shows a differential output circuit based on the conventional art. This differential output circuit comprises two n-channel MOS transistors (hereafter called nMOS transistor) M1 and M3, two p-channel MOS transistors (hereafter called pMOS transistor) M2 and M4, two constant current sources J1, J2, and drivers IN1, IN2, BU1, and BU2. The drivers IN1, IN2, BU1, and BU2 receive a common input signal X to generate control signals A1, A2, B1, and B2 to be applied to respective gate electrodes of the MOS transistors M1 to M4. When the input signal X is at a low level (hereafter called L level), the transistors M1 and M4 are turned on, while the transistors M2 and M3 are turned off. Conversely, when the input signal X is at a high level (hereafter called H level), the transistors M1 and M4 are turned off, while the transistors M2 and M3 are turned on. Accordingly, logical signals Y1 and Y2 in opposite phases to each other are output from nodes N1 and N2, respectively.
The output signals Y1 and Y2 are transferred to circuits of another semiconductor chip through respective transmission paths 1 and 2. A resistor R is connected between the nodes N1 and N2 to perform a function as a terminator resistor with respect to the transmission paths 1 and 2.
Each of the drivers IN1 and IN2 is a CMOS inverter circuit that outputs an inverted logic of an input signal X. Each of the drivers BU1 and BU2 consists of two CMOS inverter circuits connected in series, and is a buffer circuit for outputting the same logic as that of an input signal X.
FIG. 2 shows respective waveforms of the control signals A1, A2, B1, and B2 and the output signals Y1 and Y2. Assume that the drivers IN1 and IN2 have changed from an H level to an L level at a time s1 in response to a change of an input signal X from an L level to an H level. Because of the difference of configuration of the drivers BU1 and BU2 from that of the drivers IN1 and IN2, the signals B1 and B2 change from the L level to the H level at a time s2 that is later than the time s1 as shown in FIG. 2.
The MOS transistor M1 changes from an on state to an off state and the MOS transistor M2 changes from an off state to an on state in response to level changes of the signals A1 and A2 at the time s1, respectively, and the voltage on the node N1 then rises from the L level. On the other hand, the MOS transistor M3 remains in the off state and the MOS transistor M4 remains in the on state until the time s2 is reached. Therefore, the potential on the node N2 also rises through the resistor R according to rising of the voltage on the node N1. Subsequently, the MOS transistors M3 and M4 change to the on state and the off state, respectively, in response to level changes of the signals B1 and B2 at the time s2, and the voltage on the node N2 drops. In response to the drop, the voltage on the node N1 momentarily drops through the resistor R, but the node N1 is driven by the MOS transistor M2 to the high voltage again.
When the signals A1 and A2 change from the L level to the H level at a time s3 in response to a change of the input signal X from the H level to the L level, the signals B1 and B2 change from the H level to the L level at a time s4 that is later than the time s3. The MOS transistor M1 changes from the off state to the on state and the MOS transistor M2 changes from the on state to the off state in response to level changes of the signals A1 and A2 at the time s3, and the voltage on the node N1 drops from the H level. On the other hand, the MOS transistor M3 remains in the on state and the MOS transistor M4 remains in the off state until the time s4 is reached. Therefore, the potential on the node N2 also drops through the resistor R according to drop of the voltage on the node N1. The MOS transistor M3 changes to the off state and the MOS transistor M4 changes to the on state in response to level changes of the signals B1 and B2 at the time s4, respectively, and the voltage on the node N2 rises. The voltage on the node N1 momentarily rises through the resistor R according to rising of the voltage on the node N2, but the node N1 is driven by the MOS transistor M1 to the low voltage again.
As explained above, the control signals A1, A2, B1, and B2 are generated so that response of the signals B1 and B2 to the input signal X is delayed as compared to response of the signals A1 and A2. Resultantly, as shown in FIG. 2, an overshoot that momentarily exceeds the voltage at the H level and an undershoot that momentarily drops lower than the voltage at the L level occur in the output signal Y2 in response to logical level changes of the input signal X. Further, a portion D1 that momentarily drops its waveform and a portion D2 that momentarily raises its waveform occur in the output signal Y1. The distortions of these waveforms are caused by occurrence of a period in which both of the MOS transistors M1 and M2 are turned off simultaneously when both of the MOS transistors M3 and M4 are turned on or by occurrence of a period in which both of the MOS transistors M3 and M4 are turned off simultaneously when both of the MOS transistors M1 and M2 are turned on according to level changes of the input signal X.
Such distortions in the output waveforms of the output signals Y1 and Y2 are not merely an apparent problem but become a problem in terms of signal propagation property. For example, although the terminator resistor R is provided, the signals Y1 and Y2 are reflected to a certain extent by the respective ends of the transmission paths 1 and 2. The reflection of the distorted portions of the waveforms causes to further disturb the waveforms of the output signals Y1 and Y2. Accordingly, signals having proper waveforms may not be transferred to their destinations. Further, if there are other transmission paths adjacent to the transmission paths 1 and 2, wiring capacity between the transmission paths 1 and 2 and the adjacent transmission paths may cause so-called cross talk noise that the distortions of these waveforms cause noise to occur on other adjacent transmission paths.
It is an object of this invention to provide a semiconductor integrated circuit that suppresses waveform distortions of output signals when logical levels of the output signals are changed in accordance with an input signal.
The semiconductor integrated circuit according to one aspect of this invention comprises a first MOS transistor of a first conductivity type having a drain terminal connected to a first node; a second MOS transistor of a second conductivity type different from the first conductivity type, having a drain terminal connected to said first node; a third MOS transistor of the first conductivity type having a drain terminal connected to a second node and a source terminal connected to a source terminal of said first MOS transistor; a fourth MOS transistor of the second conductivity type having a drain terminal connected to said second node and a source terminal connected to a source terminal of said second MOS transistor; and a driver circuit which generates first to fourth control signals whose logical levels change in response to a common input signal, and applies the signals to respective gate terminals of said first to fourth MOS transistors. In this structure, the first control signal starts to change from a low level to a high level at a first time in response to a first level change of the input signal from a high level to a low level, and starts to change from the high level to the low level at a second time in response to a second level change of the input signal from the low level to the high level. The second control signal starts to change from a low level to a high level at a third time, that is later than the first time, in response to the first level change of the input signal, and starts to change from the high level to the low level at a fourth time, that is earlier than the second time, in response to the second level change of the input signal. The third control signal starts to change from a high level to a low level at a fifth time in response to the first level change of the input signal, and starts to change from the low level to the high level at a sixth time in response to the second level change of the input signal. The fourth control signal starts to change from a high level to a low level at a seventh time, that is earlier than the fifth time, in response to the first level change of the input signal, and starts to change from the low level to the high level at an eighth time, that is later than the sixth time, in response to the second level change of the input signal. Moreover, at least a portion of a period between the first and second times and at least a portion of a period between the fifth and sixth times overlap one another, and at least a portion of a period between the third and fourth times and at least a portion a period between the seventh and eighth times overlap one another.
The semiconductor integrated circuit according to one aspect of this invention comprises a first MOS transistor of a first conductivity type having a drain terminal connected to a first node; a second MOS transistor of a second conductivity type different from said first conductivity type, having a drain terminal connected to said first node; a third MOS transistor of the first conductivity type having a drain terminal connected to a second node and a source terminal connected to a source terminal of said first MOS transistor; a fourth MOS transistor of the second conductivity type having a drain terminal connected to said second node and a source terminal connected to a source terminal of said second MOS transistor; and a driver circuit. This driver circuit generates first and second control signals each of which changes from a low level to a high level in response to a first level change of an input signal from a high level to a low level, and changes from the high level to the low level in response to a second level change of the input signal from the low level to the high level; and third and fourth control signals each of which changes from a high level to a low level in response to the first level change of the input signal, and changes from the low level to the high level in response to the second level change of the input signal. The driver circuit applies the first to fourth control signals to respective gate terminals of said first to fourth MOS transistors. The driver circuit includes at least one first logic circuit consisting of a first delay circuit that is connected to a node whose voltage at its input changes in response to a voltage change of the input signal and delays the voltage change at the input to be output; and a NAND logic gate whose first input is connected to the input of said first delay circuit, and whose second input is connected to the output of said first delay circuit, and which outputs a NAND logic; and at least one second logic circuit consisting of a second delay circuit that is connected to a node whose voltage at its input changes in response to a voltage change of the input signal and delays the voltage change at the input to be output; and a NOR logic gate whose first input is connected to the input of said second delay circuit, and whose second input is connected to the output of said second delay circuit, and which outputs a NOR logic. The driver circuit generates the first to fourth control signals based on the NAND logic output from at least one first logic circuit and the NOR logic output from at least one second logic circuit.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.